1. Field of the Invention
This invention relates to a semiconductor device, specifically to a transistor structure to improve an ESD (Electro Static Discharge) withstand voltage.
2. Description of the Related Art
A DMOS (Diffused MOS) type MOS transistor has a high source-drain withstand voltage and a high gate withstand voltage, and is used in various kinds of drivers such as an LCD driver, power supply circuits and the like. In particular, a high withstand voltage MOS transistor having a low ON resistance as well as a high drain withstand voltage (BVds) is required in recent years.
FIG. 6 is a cross-sectional view showing a conventional N-channel type high withstand voltage MOS transistor. An epitaxial layer 101 of N−−-type is formed in a surface of a P-type semiconductor substrate 100. An N-type buried layer 102 is formed at an interface between a bottom of the epitaxial layer 101 and the semiconductor substrate 100. The epitaxial layer 101 is divided into a plurality of isolated regions with insulating isolation layers. The insulating isolation layer is composed of contiguously disposed P-type impurity doped layers of an upper isolation layer 103 and a lower isolation layer 104.
A gate insulation film 105 and a thick field insulation film 106 are formed on the epitaxial layer 101. A gate electrode 107 is formed on the gate insulation film 105 and on an adjacent portion of the field insulation film 106. A P-type body layer 108 is formed in a surface of the epitaxial layer 101. A high impurity concentration (N+) source layer 109 is formed in a surface of the body layer 108 adjacent one end of the gate electrode 107.
A high impurity concentration (N+) drain layer 110 is formed in the surface of the epitaxial layer 101 separated from the other end of the gate electrode 107. A low impurity concentration (N−) drain layer 111 that is lower in impurity concentration and deeper in diffusion depth than the high impurity concentration drain layer 110 is formed in a region extending from beneath the gate electrode 107 to beneath the high impurity concentration drain layer 110. The high impurity concentration drain layer 110 is formed in the low impurity concentration drain layer 111.
An electric potential fixing layer 112 into which P-type impurities are implanted is formed in the surface of the body layer 108 adjacent the source layer 109. The electric potential fixing layer 112 is a layer to fix an electric potential of the body layer 108.
An interlayer insulation film 113 is formed over entire surface of the semiconductor substrate 100. Contact holes reaching the gate electrode 107, the source layer 109, the electric potential fixing layer 112 and the high impurity concentration drain layer 110 are formed in the interlayer insulation film 113. A source electrode 114 and a drain electrode 115 are formed on the corresponding contact holes respectively. The source electrode 114 is usually connected to a VSS wiring (ground voltage). Note that the contact hole reaching the gate electrode 107 and a metal layer in the contact hole are omitted in FIG. 6.
A surface region of the body layer 108 between the epitaxial layer 101 and the source layer 109 makes a channel region CH. The semiconductor substrate 100 is not connected with the source electrode 114 and is not grounded.
When an excessive positive surge voltage is applied to the source electrode 114 (or an excessive negative surge voltage is applied to the drain electrode 115) of the conventional semiconductor device 120, a parasitic diode 121, which is composed of the P-type body layer 108 as an anode and the N-type drain layer as a cathode as shown in FIG. 6, is turned on and thereby an ESD current flows from the source electrode 114 to the drain electrode 115. Also, a parasitic diode 122, which makes a current path from the body layer 108 through the buried layer 102 to the drain electrode 115, is turned on.
Furthermore, when the semiconductor substrate 100 is connected with the VSS wiring (ground wiring) similar to the source electrode 114, a parasitic diode 123, which is composed of the P-type semiconductor substrate 100 as an anode and the N-type buried layer 102 and the drain layer as a cathode, is turned on and thereby a current flows to the drain electrode 115. The transistor structure, in which the parasitic diode 123 is turned on in addition to the parasitic diodes 121 and 122 as described above, is called a semiconductor device 125.
Technologies described above are disclosed in Japanese Patent Application Publication No. 2004-39774.
With the transistor structure described above, however, there is a problem that an electrostatic discharge damage is caused between the source and the drain when the excessive positive surge voltage is applied to the source electrode (or an excessive negative surge voltage is applied to the drain electrode). That is, an electrostatic discharge withstand voltage (hereafter referred to as ESD withstand voltage) is not enough with the conventional structure. For example, according to typical electrostatic discharge damage tests based on a machine model (MM) conducted by the inventor, the ESD withstand voltage of the semiconductor device 120 is about 130 volts and the ESD withstand voltage of the semiconductor device 125 is about 180 volts as shown in FIG. 4, which are not high enough. Therefore, this invention is directed to offering a transistor structure that improves the ESD withstand voltages.